Adder circuit apparatus

ABSTRACT

An adder circuit includes a Manchester-carry-chain circuit which propagates a carry signal for each block consisting of plural bits, and a carry-look-ahead circuit which selects said carry signal in response to a carry propagation signal being generated by a full adder, and when the carry signal is not generated in the two consecutive blocks, an output from the Manchester-carry-chain circuit is selected by the carry-look-ahead circuit, so that the carry signal being inputted to the low-order block of the two blocks can be propagated as the carry signal to be outputted from the high-order block.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an adder circuit apparatus in whichserial plural-digit full adders are arranged in blocks, moreparticularly, it relates to an adder circuit apparatus including aManchester-carry-chain circuit with a carry-look-ahead circuit as acarry signal propagation circuit.

2. Description of Related Art

A conventional full adder and a Manchester-carry-chain circuit aredescribed, for example, on pages 324, 325, in "PRINCIPLES OF CMOS VLSIDESIGN" by Neil H. E. Weste and Kamran Eshraghian, published byAddison-Wesley Publishing Corp. FIGS. 1 and 2 illustrate circuitdiagrams showing the configuration of the prior art full adder andManchester-carry-chain circuit described in the aforesaid book. In FIG.1, an i th bit addend input signal A_(i) and an augend input signalB_(i) are given to a NAND circuit 1_(a) and an NOR circuit 2_(a)respectively. An output signal of the NAND circuit 1_(a) is given to oneend of a NAND circuit 1_(b) and is outputted as a carry generationsignal G_(i) via an inverter 3_(e). An output signal of the NOR circuit2_(a) is given to the other end of the NAND circuit 1_(b) via aninverter 3_(f). An output signal of the NAND circuit 1_(b) is outputtedas a carry propagation signal P_(i) via an inverter 3_(g) and is givento one end of an exclusive (hereinafter referred to as Ex) NOR circuit4. An i-1 th bit inversion carry output signal (hereinafter referred toas a carry signal) C_(i-1) is given to the other end of the ExNORcircuit 4, of which output signal is outputted as an i th bit sum outputsignal S_(i).

In FIG. 2, numeral 7 indicates a 4-bit Manchester-carry-chain circuit,which comprises five P channel transistor (hereinafter referred to asPchTR) 5_(a0), 5_(a1) . . . 5_(a4) whose sources are connected to apower supply, five N channel transistors (hereinafter referred to asNchTR) 6_(a0), 6_(a1) . . . 6_(a4) whose drains are connected to eachdrain of said PchTRs 5_(a0), 5_(a1) . . . , five NchTRs 6_(b0), 6_(b1) .. . 6_(b4) whose drains are connected to the sources of said NchTRs6_(a0), 6_(a1) . . . 6_(a4) respectively and whose sources are earthed,four NchTRs 6_(g1), 6_(g2), 6_(g3), 6_(g4) whose sources are connectedto intermediate nodes between the PchTRs 5_(a0) ˜5_(a3) and the NchTRs6_(a0) ˜6_(a3), and whose drains are connected to intermediate nodesbetween the PchTRs 5_(a1) ˜5_(a4) and the NchTRs 6_(a1) ˜6_(a4) and aninverter 3_(a1) which outputs a 4-bit carry signal C₄. There are given aclock signal CLK to the gates of the PchTRs 5_(a0), 5_(a1) . . . andNchTRs 6_(b0), 6_(b1) . . . , a first carry signal C₀ to the gate of theNchTR 6_(a0), and carry generation signals G₁, G₂ . . . for each bit tothe gates of the NchTRs 6_(a1), 6_(a2) . . . , respectively. Carrypropagation signals P₁, P₂ . . . for each bit are given to the gates ofthe NchTRs 6_(g1), 6_(g2) . . . . The intermediate node between thePchTR 5_(a0) and NchTR 6_(a0) and that between the PchTR 5_(a4) andNchTR 6_(a4) are connected via an NchTR 6_(L1).

Numeral 9 denotes a carry-look-ahead circuit, which comprises, a clockedAND circuit 8 provided in every block each consisting of 4 bits, and inwhich a PchTR 5_(b1) and the NchTRs 6_(c1), 6_(c2), 6_(c3), 6_(c4)connected to a power supply at their sources and an NchTR 6_(d1) earthedat its source are connected in series, and an inverter 3_(b1) isconnected to an intermediate node between the PchTR 5_(b1) and NchTR6_(c1), and the aforesaid NchTR 6_(L1). Output of the inverter 3_(b1) isgiven to a gate of the NchTR 6_(L1), so is the clock signal CLK to agate of the NchTR 6_(d1). To gates of the NchTRs 6_(c1), 6_(c2), 6_(c3),6_(c4), carry propagation signals P₁, P₂, P₃, P₄ for each bit are givenseparately.

In the following, the operation of the conventional adder circuit thusconstructed will be described. Table 1 below shows a truth table of thefull adder shown in FIG. 1.

                  TABLE 1                                                         ______________________________________                                         A.sub.i                                                                              B.sub.i   G.sub.i                                                                             P.sub.i                                                                                 ##STR1##                                                                           S.sub.i                                ______________________________________                                        0      0         0     0         0    1                                                                        1    0                                       0      1         0     1         0    0                                                                        1    1                                       1      0         0     1         0    0                                                                        1    1                                       1      1         1     0         0    1                                                                        1    0                                       ______________________________________                                    

As it will be apparent from the Table 1, a carry generation signal G_(i)becomes "1" when both the addend input signal A_(i) and the augend inputsignal B_(i) are "1". Also, a carry propagation signal P_(i) becomes "1"when the addend input signal A_(i) and the augend input signal B_(i)show the different values.

Meanwhile, in FIG. 2, because the PchTRs 5_(a0) ˜5_(a4) and 5_(b1) areON and the NchTRs 6_(b0) ˜6_(b4) and 6_(d1) are OFF when the clocksignal CLK is "0", the inversion carry signal C_(i) of each bit becomes"1" respectively by a power supply voltage.

When the clock signal CLK becomes "1" and the carry generation signalG_(i) is "1", the inversion carry signal C_(i) becomes "0" and the carrysignal C_(i) is generated. At that time, if the carry propagation signalP_(i) is "1", the NchTR 6_(gi) to which the carry propagation signalP_(i) is inputted is turned on, and the (i-1)th bit inversion carrysignal C_(i-1) is propagated as the i th bit inversion carry signalC_(i). This inversion carry signal C_(i) is added to the addend inputsignal A_(i+1) and the augend input signal B_(i+1) in the full adder ofthe (i+1)th bit, thereby a sum output signal S_(i+1) is obtained.

While, when the clock signal CLK becomes "1" and all of the carrypropagation signal P_(i) are "1", the output signal from the inverter3_(b1) in the clocked AND circuit 8 of the carry-look-ahead circuit 9becomes "1" and the NchTR 6_(L1) is turned on, thereby the firstinversion carry signal C₀ of the Manchester-carry-chain circuit 7 ispropagated directly as the 4th bit inversion carry signal C₄.

A maximum delay path with the longest propagation time of carry signalof the circuit shown in FIG. 2 will now be considered.

Firstly, when the carry signal C₀ and the carry propagation signals P₁˜P₄ are "1", though the first inversion carry signal C₀ is propagated asthe inversion carry signal C₄ via the 4-step NchTRs 6_(g1) ˜6_(g4), atthis time the NchTR 6_(L1) is turned on by the carry-look-ahead circuit9, allowing it to propagate also via the 1-step NchTR 6_(L1), then, thiswill not be the maximum delay path.

When the carry generation signal G₁ and the carry propagation signals P₂˜P₄ are "1", however, since the inversion carry signal C₁ is propagatedvia the 3-step NchTRs 6_(g2) ˜6_(g4), this will be the maximum delaypath of the Manchester-carry-chain circuit 7.

Next will be described a maximum delay path of the carry signal when theadder circuits are aligned in plural steps as shown in FIG. 2.

FIG. 3 is a circuit diagram showing the configuration of a conventional32-bit adder circuit, in which eight 4-bit Manchester-carry-chaincircuits shown in FIG. 2 are connected in series. Here j indicates ablock, 6_(Lj) denotes an NchTR in the j th block carry-look-aheadcircuit 9 from the low-order, C_(i) designates an i th bit carry signal,so does C_(i) an i th bit inversion carry signal.

When the carry signal generated in the low-order is propagated as thetop-order carry signal, the number of NchTRs interposed therebetweenincreases to become a maximum delay path.

The maximum delay path in the adder circuit constructed as shown in FIG.3 is attained by propagating the carry signal C₁ generated in the firstbit as the 32nd bit carry signal C₃₂. That is, it is the case when thecarry generation signal G₁ and the carry propagation signals P₂ ˜P₂₂ are"1". In this case, the inversion carry signal C₁ is propagated as thecarry signal C₄ via the 3-step NchTRs 6_(g2) ˜6_(G4) and a 1-stepinverter 3_(a), and then is propagated as the carry signal C₃₂ via the7-step NchTRs 6_(L2) ˜6_(L8) and 14-step inverters 3_(a), 3_(b) . . . ofthe carry-look-ahead circuits 9, 9 . . . present at intervals of fourbits. Thus, when the maximum delay path is passed, the carry signal C₁is propagated via the total of 10-step NchTRs and 15-step inverters.

In such a prior art adder circuit as described above, when a low-orderdigit carry signal is propagated directly to the high-order digit, ithas to pass all of the carry-look-ahead circuit gates in the higherorder than the propagation starting digit, thus, the propagation time ofthe carry signal is considerably delayed to hinder the high-speedoperation.

SUMMARY OF THE INVENTION

The present invention has been devised in view of such circumstances,and, it is a primary object thereof to provide an adder circuitapparatus in which when a low-order digit carry signal is propagateddirectly to the high-order digit, carry-look-ahead circuit gates locatedin the higher order than the propagation starting digit are passedalternately to reduce the number of gate steps to be passed on thepropagation path of the carry signal, and to shorten the propagationtime delay thereof for realizing the high-speed operation.

In order to accomplish the object, in the adder circuit apparatusaccording to the present invention, operating means for executing theAND operation of a carry propagation signal in a block is provided, anda carry signal generated by carry signal propagating means in the blockis outputted as a carry output signal when the operation result isfalse, and a carry input signal inputted to the carry signal propagatingmeans in the block is outputted as a carry output signal of the blockwhen the operation result is true, and a carry input signal to alow-order block is outputted as the carry output signal of the blockwhen the operating means is true and the operation result of operatingmeans of the adjoining block in the low-order is true.

As a result, when the operation result of the operating means is truefor two consecutive blocks, a carry input signal to the low-order blockis outputted as a carry output signal of the high-order block, and thecarry signal is propagated via the block gate alternately, then, thenumber of gates to be passed at propagation is reduced.

The above and further objects and features of the invention will morefully be apparent from the following detailed description withaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the configuration of a conventionalfull adder,

FIG. 2 is a circuit diagram showing the configuration of a conventionaladder circuit apparatus,

FIG. 3 is a circuit diagram showing the configuration of a conventional32-bit adder circuit,

FIG. 4 is a circuit diagram showing the configuration of an addercircuit according to the present invention,

FIG. 5 is a circuit diagram showing the configuration of a full adderemployed therein,

FIG. 6 is a circuit diagram showing the configuration of a 32-bit addercircuit apparatus,

FIG. 7 is a circuit diagram showing the configuration of a modified32-bit adder circuit apparatus,

FIG. 8 is a circuit diagram showing the configuration of an addercircuit apparatus of another embodiment,

FIG. 9 is a circuit diagram showing the configuration of a 32-bit addercircuit apparatus of another embodiment, and

FIG. 10 is a circuit diagram showing the configuration of a modified32-bit adder circuit apparatus of another embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments of the present invention will be describedwith reference to the drawings. FIG. 4 is a circuit diagram showing theconfiguration of an adder circuit apparatus according to the presentinvention, and FIG. 5 is a circuit diagram showing the configuration ofa full adder used therein. In FIG. 5, an addend input signal A_(i) andan augend input signal B_(i) are given to a NOR circuit 2_(b) as well asto an ExOR circuit 10_(a). An output signal of the NOR circuit 2_(b) isoutputted as a carry delete signal K_(i), and an output signal of theExOR circuit 10_(a) is outputted as a carry propagation signal P_(i) aswell as to one end of the ExOR circuit 10_(b). To the other end of theExOR circuit 10b, a carry signal C_(i-1) which is a 1-bit low-ordercarry output signal is given, and this output signal is outputted as asum output signal S_(i).

In FIG. 4, numeral 7 indicates a 4-bit precharge-typeManchester-carry-chain circuit in a second block of 5th to 8th bit, saidManchester-carry-chain circuit 7 comprising four PchTRs 5_(a5), 5_(a6) .. . 5_(a8) whose sources are connected to a power supply, four NchTRs6_(a5), 6_(a6) . . . 6_(a8) whose drains are connected to the respectivedrains of the PchTRs 5_(a5), 5_(a6) . . . , four NchTRs 6_(b5), 6_(b6) .. . 6_(b8) whose drains are connected to the sources of the NchTRs6_(a5), 6_(a6) separately and whose sources are earthed, and four NchTRs6_(g5), 6_(g6) . . . 6_(g8) connected in series and provided withone-bit low-order carry signal C₄ in its source at the LSB side. Drainsof NchTR 6_(gi) and PchTR 5_(ai) of each bit i are connected. To thegates of the PchTRs 5_(a5) ˜5_(a8) and NchTRs 6_(b5) ˜6_(b8), a clocksignal CLK is given, and carry propagation signals P₅ ˜P₈ for each bitare given separately to the gates of the NchTRs 6_(g5) ˜6_(g8).

Carry signals C₄ ˜C₇ are propagated as a carry signal C₈ when the carrypropagation signals P₅ ˜P₈ are "1". To the gates of the NchTRs 6_(a5)˜6_(a8), carry delete signals K₅ ˜K₈ which are the associated carrysignal of each bit are given, and when the signals K₅ ˜K₈ are "1", thecarry signals C₅ ˜C₈ become "0" and are deleted.

Numeral 9 denotes a carry-look-ahead circuit, which comprises a clockedAND circuit 8 consisting of a PchTR 5_(b2) and five NchTRs 6_(c5)˜6_(c8), 6_(d2) connected in series and whose one end is connected to apower supply and whose other end is earthed, and an inverter 3_(b2)connected to an intermediate node between the PchTR 5_(b2) and the NchTR6_(c5), an inverter 3_(c2) for inversing a 1-bit low-order carry signalC₄ and transmitting it to a high-order block, and five NchTRs 6₂₁ ˜6₂₅.To the gates of the PchTR 5_(b2) and NchTR 6_(d2) in the clocked ANDcircuit 8, the clock signal CLK is given, and to the gates of fourNchTRs 6_(c5) ˜6_(c8), carry propagation signals P₅ ˜P₈ of each bit aregiven separately.

The NchTR 6₂₁ and NchTR 6₂₂ are connected in series, and a drain of theNchTR 6₂₁ is connected to an intermediate node between the PchTR 5_(a8)and NchTR 6_(a8), and a source of the NchTR 6₂₂ is earthed. To a gate ofthe NchTR 6₂₁, 1-bit low-order inversion carry signal C₄ which is anoutput signal of the inverter 3_(c2) is given, and to a gate of theNchTR 6₂₂, an output signal AP_(U) of the clocked AND circuit 8 which isan output of the inverter 3_(b2) is given.

The NchTRs 6₂₃, 6₂₄, 6₂₅ are connected in series, and a drain of theNchTR 6₂₃ is connected to a drain of the NchTR 6₂₁, and a source of theNchTR 6₂₅ is earthed. There are given to a gate of the NchTR 6₂₃, aninversion carry signal C₀ which is a one-block low-order (1st to 4thbit) inversion carry input signal of the Manchester-carry-chain circuit7 aligned in every block consisting of 4 bits, an output signal AP_(L)of the one-block low-order clocked AND circuit 8 to a gate of the NchTR6₂₄, and the output signal AP_(U) of the clocked AND circuit 8 of theblock to a gate of the NchTR 6₂₅.

The operation of the full adder and the adder circuit apparatusconstructed as aforementioned will be described below. Table 2 belowshows a truth table of the full adder shown in FIG. 5.

                  TABLE 2                                                         ______________________________________                                         A.sub.i                                                                              B.sub.i   K.sub.i                                                                             P.sub.i                                                                                 ##STR2##                                                                           S.sub.i                                ______________________________________                                        0      0         1     0         0    0                                                                        1    1                                       0      1         0     1         0    1                                                                        1    0                                       1      0         0     1         0    1                                                                        1    0                                       1      1         0     0         0    0                                                                        1    1                                       ______________________________________                                    

As it will be apparent from the above Table 2, a carry delete signalK_(i) becomes "1" when both of the addend input signal A_(i) and theaugend input signal B_(i) are "0". Also, a carry propagation signalP_(i) becomes "1" when the addend input signal A_(i) and the augendinput signal B_(i) show the different values.

In FIG. 4, when the clock signal CLK is "0", the PchTRs 5_(a5) ˜5_(a8)and PchTR 5_(b2) are turned on, and the carry signal C_(i) as the carryoutput signal of each bit is precharged by a power supply voltage andbecomes "1" respectively.

Next, when the clock signal CLK becomes "1" and the carry delete signalK_(i) is "1", an NchTR 6_(ai) whose gate receives the carry deletesignal K_(i) is turned on and the charged carry signal C_(i) isdischarged, becoming "0" and deleted. In this case, when the i th bitcarry propagation signal P_(i) is "1", that is, in the third condition,the NchTR 6_(gi) whose gate receives the carry propagation signal P_(i)is turned on, and the (i-1)th bit carry signal C_(i-1) is propagated asthe i th bit carry signal C_(i). The carry signal C_(i), in the (i+1)thbit full adder, is added with an addend input signal A_(i+1) and anaugend input signal B_(i+1), thereby a sum output signal S_(i+1) isobtained.

And when the clock signal CLK becomes "1" and all of the carrypropagation signals P₅ ˜P₈ are "1", that is, in the first condition, theoutput signal AP_(U) of the clocked AND circuit 8 in thecarry-look-ahead circuit 9 becomes "1" and the NchTR 6₂₂ is turned on.At that time, if the carry signal C₄ is "0", the inversion carry signalC₄ becomes "1" and the NchTR 6₂₁ is turned on. The carry signal C₈ as acarry output signal is discharged and becomes "0". Also, at that time,if the carry signal C₄ is "1", the NchTR 6₂₁ remains to be OFF and thecarry signal C₈ is not discharged and remains to be "1". Accordingly, inthe first condition, a potential of the carry signal C₈ becomes equal tothat of the carry signal C₄, which is propagated directly as the carrysignal C₈.

Now, viewing the case of the second condition where all of the carrypropagation signals P₅ ˜P₈ of the high-order adder circuit and the carrypropagation signals P₁ ˜P₄ of the low-order adder circuit are coincidedwith "1" in the configuration wherein adder circuit apparatus arealigned in two steps as shown in FIG. 4, that is, the case where all ofthe carry propagation signals are "1" for the serial 8-bit full adders,in this case, an AND signal of the low-order 4-bit carry propagationsignals P₁ ˜P₄ corresponds to the output signal AP_(L) in the high-orderadder circuit, which signal becomes "1" (=truth). Since the outputsignal AP_(U) which is an "and" of the high-order 4-bit carrypropagation signals P₅ ˜P₈ also becomes "1" (=truth), both of the NchTR6₂₄ and the NchTR 6₂₅ are turned on. In this case, when the carry signalC₀ is "0", since the inversion carry signal C₀ becomes "1" and the NchTR6₂₃ is turned on and all of the three NchTRs 6₂₃ ˜ 6₂₅ are turned on,the carry signal C₈ is discharged and becomes "0". When the carry signalC₀ is "1", the NchTR 6₂₃ remains to be off and the carry signal C₈ isnot discharged and remains to be "1". Accordingly, a potential of thecarry signal C₈ becomes equal to that of the carry signal C₀, and thefirst carry signal C₀ is directly propagated as the carry signal C₈. Atthat time, the first condition aforementioned is met in the low-orderblock, then, the carry signal C₄ shows the same potential as the carrysignal C₀.

Now will be described below a maximum delay path of the carry signalwhen the adder circuit apparatus are aligned in plural steps as shown inFIG. 4. FIG. 6 is a circuit diagram showing the configuration of a32-bit adder circuit apparatus of the present invention, in which eight4-bit Manchester-carry-chain circuits shown in FIG. 4 are connected inseries.

The maximum delay path in this case occurs when a carry signal generatedin the lower order is propagated as the top-order carry signal. In theconfiguration shown in FIG. 6, the maximum delay path occurs when acarry signal C₁ generated in the first bit is propagated as a 32nd bitcarry signal C₃₂. That is, it occurs when the carry delete signal K₁ is"0" and the carry propagation signals P₂ ˜P₃₂ are "1". In this case, thecarry signal C₁ is propagated to the first block as the carry signal C₄via the 3-step NchTRs 6_(g2) ˜6_(g4), and then is directly propagated atevery eight bits as the carry signal C₁₂, C₂₀, C₂₈ via the inverters3_(c2), 3_(c4), 3_(c6), 3_(c8) and the NchTRs 6₃₃, 6₅₃, 6₇₃, 6₈₁ (6₅₃,6₇₃ are not shown) in the carry-look-ahead circuit 9, and is propagatedas the top-order digit carrier signal C₃₂. As previously described, thecarry signal C₁ is propagated via the 4-step NchTRs 6₃₃, 6₅₃, 6₇₃, 6₈₁and the 4-step inverters 3_(c2), 3_(c4), 3_(c6), 3_(c8) in thecarry-look-ahead circuit 9, then, it passes through both of the 7-stepNchTRs including the 3-step NchTRs 6_(g2) ˜6_(g4) in the first block andthe 4-step inverters.

A modification of the embodiment will now be described.

FIG. 7 is a circuit diagram showing the configuration of a modifiedadder circuit, in which the carry-look-ahead circuit shown in FIG. 4 isprovided in the Manchester-carry-chain circuits 7, 7 . . . of evennumbers of blocks (j=2, 4, 6, 8). Then, the carry-look-ahead circuit 9of odd numbers of blocks (j=1, 3, 5, 7) consists of the clocked ANDcircuit 8 and the inverter 3_(cj), and the output signal AP_(U) of theclocked AND circuit 8 in the odd numbers of blocks is given to the gateof the NchTR 6_(j4) in its high-order even numbers of blocks, so is theoutput of the inverter 3_(cj) to the gate of the NchTR 6_(j3) in itshigh-order even numbers of blocks, respectively.

The output signal AP_(U) of the clocked AND circuit 8 of the evennumbers of blocks is not outputted to the next block but given only tothe gates of the NchTRs 6_(j2), 6_(j5), and an output signal C₄·(j-1) ofthe inverter 3_(cj) is given to the gate of the NchTR 6_(j1). A maximumdelay path of the modified embodiment thus constructed will bedescribed.

Also in this case, as same as in the case in FIG. 6, the maximum delaypath occurs when the carry signal C₁ generated in the first bit ispropagated as the 32nd bit carry signal C₃₂. And at that time, the carrysignal C₁ is propagated as the carry signal C₈ via the 3-step NchTRs6_(g2) ˜6_(g4) and the inverter 3_(c2) and NchTR 6₂₁ in thecarry-look-ahead circuit 9, and then is directly propagated at everyeight bits as the carry signals C₁₆, C₂₄, C₃₂ via the 3-step inverters3_(c3) 3_(c5), 3_(c7) in the carry-look-ahead circuit 9 of the 3rd, 5thand 7th blocks, and the 3-step NchTRs 6₄₃, 6₆₃, 6₈₃ of the 4th, 6th and8th blocks. As previously described, the carry signal C₁ is propagatedvia the 4-step NchTRs 6₂₁, 6₄₃, 6₆₃ , 6₈₃ and the 4-step inverters3_(c2), 3_(c3), 3_(c5), 3_(c7) in the carry-look-ahead circuit 9. Then,when the maximum delay path is passed, it passes through the total of7-step NchTRs and the 4-step inverters.

In the modified embodiment, the number of transistors being used isreduced and the cost is less expensive as compared with the embodimentshown in FIG. 4.

In the following, another embodiment of an adder circuit apparatus ofthe present invention will be described.

In the embodiment described heretofore, there has been described on theadder circuit comprising the carry-look-ahead circuit 9 including theclocked AND circuit 8, and the precharged-type Manchester-carry-chaincircuit, however, in this embodiment, a static-typeManchester-carry-chain circuit and the carry-look-ahead circuit areemployed. Accordingly, a clock is not necessary to be provided forcontrol. Though the static-type Manchester-carry-chain circuit has aslower operating speed than that of the dynamic-type, it requires noprecharging, which results in a low power consumption.

FIG. 8 is a circuit diagram showing the configuration of an addercircuit of another embodiment. In FIG. 8, numeral 12 indicates a 4-bitstatic-type Manchester-carry-chain circuit of the second block of5th˜8th bit. In the Manchester-carry-chain circuit 12 comprising fourNchTRs 6_(g5) ˜6_(g8) connected in series, the 1-bit low-order carrysignal C₄ is given to the PchTRs 5_(ci), 5_(di), NchTRs 6_(ei), 6_(fi)of each bit (i=5˜8) connected in series and a source at the LSB side.Sources of the PchTR 5_(ci) are connected to a power supply, sources ofthe NchTR 6_(fi) are earthed and drains of the NchTR 6_(gi) areconnected to the intermediate nodes between the PchTR 5_(di) and NchTr6_(ei).

To the gates of the PchTRs 5_(ci), 5_(di), the addend input signal A_(i)and the augend input signal B_(i) of each bit are given separately. Andthose signals A_(i) and B_(i) are also given to the NchTRs 6_(fi),6_(ei), respectively.

Numeral 13 denotes the static-type carry-look-ahead circuit comprising,a NAND circuit 14_(a2) which is provided with 4-bit carry propagationsignals P₅ ˜P₈ and executes the NAND operation, a NOR circuit 15_(a2)which is provided with an inversion output signal AP_(U) of the NANDcircuit 14_(a2) and an inversion output signal AP_(L) of a 1-blocklow-order NAND circuit 14_(a1) and executes the NOR operation, a NORcircuit 15_(b2) which is provided with the inversion output signalAP_(U) and the output signal AP_(L) given via an inverter 3_(d2) andexecutes the NOR operation, an NchTR 6_(i2) which propagates a carrysignal C₀ being inputted to a 1-block low-order adder circuit, a NchTR6_(h2) which propagates the carry signal C₄ outputted from the 1-blocklow-order adder circuit, and a NchTR 6_(j2) which propagates a carrysignal C₈ being outputted from the block. There are given the inversionoutput signal AP_(U) to the gate of the NchTR 6_(j2), the output signalof the NOR circuit 15_(b2) to the gate of the NchTR 6_(h2), and theoutput signal of the NOR circuit 15_(a2) to the gate of the NchTR6_(i2), respectively. Each carry signal is propagated to the followingblocks when these signals are "1". Also the carry signal C₄ is directlypropagated to the NchTR 6_(i3) of the 1-block high-order adder circuit.

The operation of the embodiment thus constructed will be described.

When all of the carry propagation signals P₅ ˜P₈ are not "1", namely, inthe third condition, that is, when the carry signal is generated in theManchester-carry-chain circuit 12, the inversion output signal AP_(U) ofthe NAND circuit 14_(a2) in the carry-look-ahead circuit 13 becomes "1",then, the NchTR 6_(j2) is turned on and the carry signal being generatedin the Manchester-carry-chain circuit 12 is propagated as the carrysignal C₈ being outputted from the block.

On the other hand, when all of the carry propagation signals P₅ ˜P₈ are"1", the inversion output signal AP_(U) of the NAND circuit 14_(a2)becomes "0". In this case, when the inversion output signal AP_(L) fromthe low-order adder circuit is "1", namely, in the first condition, theoutput signal of the NOR circuit 15_(b2) becomes "1", then, the NchTR6_(h2) is turned on and the carry signal C₄ is directly propagated asthe carry signal C₈. When the inversion output signal AP_(L) is "0",namely, in the second condition, the output signal of the NOR circuit15_(a2) becomes "1", then, the NchTR 6_(i2) is turned on and the carrysignal C₀ is directly propagated as the carry signal C₈.

FIG. 9 is a circuit diagram showing the configuration of a 32-bit addercircuit apparatus, in which eight 4-bit Manchester-carry-chain circuitshown in FIG. 8 are connected in series.

As same as in the aforesaid embodiment, a maximum delay path of thisembodiment occurs when the carry signal C₁ is generated in the firstblock and is propagated as the carry signal C₃₂, and in this case, thecarry propagation signals P₂ ˜P₃₂ become "1", then, all of the inversionoutput signals of the NAND circuits 14_(a2) ˜14_(a8) become "0" and theNOR circuit 15_(b2) and the NOR circuits 15_(a3) ˜15_(a8) are turned on.Also the NchTRs 6_(g2) ˜6_(g4), 6_(j1) are turned on and the carrysignal C₁ is propagated as the carry signal C₄ via the four NchTRs6_(g2) ˜6_(g4), 6_(j1), which signal is further propagated as the carrysignal C₈ via the NchTR 6_(h2), then being propagated as the carrysignals C₁₆, C₂₄, C₃₂ via the NchTRs 6_(i4), 6_(i6), 6_(i8).Accordingly, in this case, the carry signal is propagated via the 8-stepNchTRs.

FIG. 10 is a circuit diagram showing the configuration of a modified32-bit adder circuit apparatus of this embodiment, in which thecarry-lock-ahead circuit shown in FIG. 8 is provided in theManchester-carry-chain circuits 7, 7 . . . of even numbers of blocks(j=2, 4, 6, 8), as same as in FIG. 7. Then, the carry-ahead-circuit 9 ofodd numbers of blocks (j=1, 3, 5, 7) consists of the NAND circuits14_(aj), and the output signal AP_(U) of the NAND circuits 14_(aj) inthe odd numbers of blocks is given to the NAND circuit 15_(aj+1) and theinverter 3_(dj+1). The carry signal C₄·j of the even blocks is notdirectly propagated to the high odd blocks. A maximum delay path of themodified another embodiment occurs when the carry signal C₁ is generatedin the first block and is propagated as the carry signal C₃₂. In thiscase the carry signal is propagated via the 8-step NchTRs, as same asthe case shown in FIG. 9.

In the two embodiments described above, there has been described aboutan example of the case where an adder circuit is divided into everyconstant digit block of four bits each, however, it will be appreciatedthat the present invention is not limited thereto, but may have theconfiguration wherein the number of digits of the block is not constant.

In the two embodiments aforementioned, the case where a positive logicalcarry signal is propagated has been described as an example, however, itis to be understood that the present invention is not limited thereto,but may also be applicable in a negative logical carry signal.

As described heretofore, according to the present invention, byproviding means for directly outputting a carry input signal to anadjoining block in the low-order as the carry output signal of theblock, in a carry-look-ahead circuit of an adder circuit comprisingserial plural-digit full adders as one block, when the carry propagationsignals in both of the block and the adjoining block in the low-orderare true, it is adapted that only the gates of the carry-look-aheadcircuits in the alternate blocks are passed when the carry signal ispropagated from the low-order to high-order blocks, reducing the numberof gates to be passed by the carry signal when it is propagated, thusthe propagation time is shortened and a high-speed procession is madepossible.

As this invention may be embodied in several forms without departingfrom the spirit of essential characteristics thereof, the presentembodiment is therefore illustrative and not restrictive, since thescope of the invention is defined by the appended claims rather than bythe description preceding them, and all changes that fall within themeets and bounds of the claims, or equivalence of such meets and boundsthereof are therefore intended to be embraced by the claims.

What is claimed is:
 1. In a multi-bit full adder including an adderblock that generates carry-bit generation and propagation signalsassociated with each bit and that utilizes a carry-chain type circuitthat responds to the carry-bit generation and propagation signals togenerate and to propagate a carry-bit, with the carry-chain circuitgrouped into serial n-bit subcircuits, each having an input forreceiving the carry-bit propagated by the immediately precedingsubcircuit and having an output for propagating a carry-bit to animmediately following subcircuit, with each subcircuit responding to thecarry-bit generation and propagation signals corresponding to therespective n bits of the full adder with each subcircuit including an APsignal generating unit for generating an AP signal indicating whether abypass condition exists where all the carry-bit propagation signalsassociated with the respective n bits are in the propagation state, witha given subcircuit comprising:a first bypass element, responsive to theAP signal generated by the given subcircuit and the carry-bit receivedat the input of the given subcircuit, for transferring the carry-bitreceived at the input of the given subscircuit to the immediatelyfollowing subcircuit only when the bypass condition exists for the givensubcircuit; and a second bypass element, responsive to the AP signalsgenerated by the given subcircuit and the immediately precedingsubcircuit and to the carry-bit received at the immediately precedingsubcircuit, for transferring the carry-bit received at the immediatelypreceding subcircuit to the immediately following subcircuit only whenthe bypass conditions exist for both immediately preceding and givensubcircuits.
 2. In an adder circuit having a plurality of adder blockscoupled in series, with each adder block having an adder block carry bitinput port coupled to an adder block carry bit output port of anadjoining lower-order adder block and having an adder block carry bitoutput port coupled to an adder block carry-bit input port of anadjoining higher-order block, with each adder block including aplurality of full adders, each full adder which receives a single-bitaddend input signal, augend input signal, and a carry signal andincludes logic elements for performing logical operations on the addend,augend, and carry input signals to generate a single-bit sum signal,associated carry-bit generation signal and carry propagation signal,with the propagation signals from the plurality of full adders includedin an adder block forming a plural-bit carry propagation signal, witheach adder block comprising:carry signal propagation means having acarry signal input coupled to the adder block carry-bit input port andhaving a carry-bit output coupled to the carry-bit adder block outputport and coupled to receive the carry-bit generation and carrypropagation signals from the plurality full adders in the adder block,for generating a single-bit carry signal in response to said associatedcarry generation signal, and for outputting and propagating the carrysignal being generated within the carry signal propagation means as anoutput carry signal to be output to the adder block carry signal inputport of an adjoining higher-order adder block in response to the carrypropagation signals being generated by said plurality of full adders ofsaid adder block; and carry signal selecting means, coupled to receivethe carry-bit signal received at the adder block carry-bit input portand to receive a carry-bit input signal received at the adder blockcarry-bit input port of an adjoining lower-order adder block, said carrysignal selecting means including operating means for executing the ANDoperation of the plural-bit carry propagation signal being generated bysaid plurality of full adders in said adder block to generate a firstcontrol signal being true when all bits of the plural-bit carrypropagation signal are true, said carry signal selecting means forselecting the carry signal being input to said adder block carry signalinput port of the adder block as the carry signal to be output to saidadjoining high-order adder block to bypass the included carry signalpropagation means, when the first control signal generated by saidoperating means is true, for selecting the carry signal being input tothe adder block carry signal input port of an adjoining lower-orderadder block as the carry signal to be output to said high-order adderblock, when said first control signal generated by said operating meansis true and a control signal, received at a control input, generated byan operating means for executing the AND operation of the plural-bitcarry propagation signal being generated by the plurality of full addersin an adjoining lower-order adder block is true, and for selecting thecarry signal being generated in said adder block as the carry signal tobe output to said adjoining high-order adder block when the firstcontrol signal generated by the operating means for executing the ANDoperation of said adder block is not true.
 3. An adder circuit as setforth in claim 2, wherein said carry signal propagating means comprisesa precharged-type Manchester-carry-chain circuit.
 4. An adder circuit asset forth in claim 3, wherein said carry signal selecting meanscomprises a carry-look-ahead circuit having a clocked AND gate as saidoperating means.
 5. In an adder circuit having a plurality of adderblocks coupled in series, with each adder block having an adder blockcarry-bit input port coupled to an adder block carry-bit output port ofan adjoining lower-order adder block and having an adder block carry-bitoutput port coupled to an adder block carry-bit input port of anadjoining higher-order block, with each adder block including aplurality of full adders each full adder which receives a single-bitaddend input signal, augend input signal, and a carry signal andincludes logic elements for performing logic operations on the addend,augend, and carry input signals to generate a single-bit sum signal,associated carry-bit generation signal and carry propagation signal,with the propagation signals from the plurality of full adders includedin an adder block forming a plural-bit carry propagation signal, witheach adder block comprising:carry signal propagation means having acarry signal input coupled to the adder block carry-bit input port andhaving a carry-bit output coupled to the carry-bit adder block outputport and coupled to receive the carry-bit generation and carrypropagation signals from the plurality of full adders in the adderblock, for generating a single-bit carry signal in response to eachassociated carry generation signal, and for outputting and propagatingthe carry signal being generated within the carry signal propagationmeans as an output carry signal to be output to the adder block carrysignal input port of an adjoining higher-order adder block in responseto the carry propagation signals being generated by said plurality offull adders of said adder block; and carry signal selecting means,coupled to receive the carry bit signal received at the adder blockcarry-bit input port and to receive a carry-bit input signal received atthe adder block carry-bit input port of an adjoining lower-order adderblock, said carry signal selecting means including operating means forexecuting the AND operation of the plural-bit carry propagation signalbeing generated by said plurality of full adders in said adder block togenerate a first control signal being true when all bits of theplural-bit carry propagation signal are true, said carry signalselecting means for selecting the carry signal being input to said adderblock carry signal input port of the adder block as the carry signal tobe output to said adjoining high-order adder block to bypass theincluded carry signal propagation means, when the first control signalgenerated by said operating means is true and a control signal, receivedat a control input, generated by an operating means for executing theAND operation of the plural-bit carry propagation signal being generatedby the plurality of full adders in an adjoining lower-order adder blockis not true, for selecting the carry signal being input to the adderblock carry signal input port of an adjoining lower-order adder block asthe carry signal to be output to said high-order adder block, when saidfirst control signal is true and a control signal, received at thecontrol input, generated by the operating means of said lower-orderadder block is true, and for selecting the carry signal being generatedin said adder block as the carry signal to be output to said adjoininghigh-order adder block when the control signal generated by theoperating means for executing the AND operation of said adder block isnot true.
 6. An adder circuit as set forth in claim 5, wherein saidcarry signal propagating means comprises a static-typeManchester-carry-chain circuit.
 7. An adder circuit as set forth inclaim 6, wherein said carry signal selecting means comprises astatic-type carry-look-ahead circuit.
 8. In an adder circuit having aplurality of pairs of adder blocks coupled in series, with the output ofthe first adder block in a pair coupled to the input of a second adderblock in a pair, with each adder block having an adder block carry bitinput port coupled to an adder block carry bit output port of anadjoining lower-order adder block and having an adder block carry bitoutput port coupled to an adder block carry-bit input port of anadjoining higher-order block, with each adder block including aplurality of full adders, each full adder which receives a single-bitaddend input signal, augend input signal, and a carry signal andincludes logic elements for performing logical operations on the addend,augend, and carry input signals to generate a single-bit sum signal,associated carry-bit generation signal and carry propagation signal,with the propagation signals from the plurality of full adders includedin an adder block forming a plural-bit carry propagation signal, witheach adder block comprising:carry signal propagation means having acarry signal input coupled to the adder block carry-bit input port andhaving a carry-bit output coupled to the carry-bit adder block outputport and coupled to receive the carry-bit generation and carrypropagation signals from the plurality full adders in the adder block,for generating a single-bit carry signal in response to said associatedcarry generation signal, and for outputting and propagating the carrysignal being generated within the carry signal propagation means as anoutput carry signal to be output to the adder block carry signal inputport of an adjoining higher-order adder block in response to the carrypropagation signals being generated by said plurality of full adders ofsaid adder block; and with the second adder block in a particular pairof adder blocks having its carry input connected to receive the carrysignal output by said carry signal propagation means of the first adderblock in the particular pair and with said second adder block in theparticular pair comprising: carry signal selecting means, coupled toreceive the carry-bit signal received at the adder block carry-bit inputport of the second adder block in the particular pair and to receive acarry-bit input signal received at the adder block carry-bit input portof the first adder block of the particular pair, said carry signalselecting means including a first operating means for executing the ANDoperation of the plural-bit carry propagation signal being generated bysaid plurality of full adders in said first adder block in theparticular pair to generate a first control signal being true when allbits of the plural-bit carry propagation signal are true, and includinga second operating means for executing the AND operation of theplural-bit carry propagation signal being generated by said plurality offull adders in said second adder block of the particular pair togenerate a second control signal being true when all bits of theplural-bit carry propagation signal are true, said carry signalselecting means for selecting the carry signal output signal generatedby the carry signal propagation means of the second adder block as thecarry bit output signal of said particular pair when the first andsecond control signals are not true, for selecting the output generatedby the carry signal propagation means of said first adder block when thefirst control signal is not true and the second control signal is trueto bypass the included carry signal propagation means of the secondadder block, and for selecting the carry signal received at the carrysignal input port of said first adder block as the carry bit outputsignal of said particular pair when the first and second control signalsare true to bypass the included carry signal generation means of thefirst and second adder blocks.